A computer programmed with appropriate computer-aided design (CAD) software, called design-rule verification tools, is normally used to verify that a design of an integrated circuit (IC) chip conforms to certain predetermined tolerances that are required in its fabrication. These predetermined tolerances are often formatted as “rules” that are used by the design-rule verification tools to confirm that the IC layout does not violate any of the design rules. The process that confirms conformance of the layout of the IC to the design rules is called “design rule check” (DRC).
Examples of DRC rules to be used in checking an IC design include minimum width, minimum spacing between elements of a circuit, minimum width of notches, checks for acute angles and self-intersecting polygons, and enclosure and overlap checks. Such DRC rules can be applied to actual layers that are to be fabricated in the chip. Such DRC rules can also be applied to layers (called “derived layers”) that are formed by logical operations (such as NOT, AND, OR, and XOR) on actual or derived layers or some combination thereof.
The goal in layout design, as always, is to reduce size and cost while improving the performance of the design. With the current trend of placing more and more transistors on a chip, this is becoming increasingly difficult. This trend results in shorter gate lengths which are more desirable to increase speed. The drawback with shorter gate lengths is that they produce more leakage.
In VLSI (Very Large Scale Integration) design, the common cell design library includes enough different cell types (latch, local clock buffer, gate level parameterized cells to name a few) to allow nearly any circuit to be implemented, avoiding the complexity of the hundreds of different macro calls that would be required by a commercial system. Traditionally, one circuit layout is considered superior to another by any one of the following reasons: circuit area, electrical characteristics, accessibility, via number (redundant contacts), timing distribution, power distribution.
Traditionally, layouts are considered valid if they satisfy the design rules whose validity has been determined by an integration team. The process is typically executed in VLSI CAD (Computer Aided Design) tools such as DRC CAD tools. (see U.S. Pat. No. 6,606,735, 2003, Richardson and Rigg: Method and system for using error and filter layers in each DRC rule). Referring to FIG. 1, there is shown an illustrative example of the traditional processing flow for a VLSI chip design. The input to the tool is the input layout in step 010. This input layout is then sent to a DRC tool in step 020 to check if the layout satisfies the design rules or it requires changes.
Once the layout is checked, for purposes of manufacturing, the design undergoes the processes of dataprep to transform the drawn shapes into mask shapes that are able to be printed by the litho tools and the resulting wafer shapes are then expected to conform to drawn shapes and the mask shapes are output in step 030.
Once a layout is declared “DRC clean,” the VLSI designer no longer plays a role in the dataprep process.
Out of necessity, integrated circuit chip size is changing, along with the computer systems in which they are housed. Computers are becoming smaller and with the decrease in size we see an increase in their processing power. Chips must be thinner and many of them are now being stacked. With this increasing density and decreasing gate lengths, it is becoming critical to address the issue of uniformity of the printed electrically equivalent gate lengths.